1. Field of the Invention
The present invention pertains to a structure and method which enables improved step coverage and reflow in copper-filled semiconductor features.
2. Brief Description of the Background Art
Due to the difficulty in etching a copper film to provide a desired semiconductor interconnect pattern, one of the preferred methods of providing copper interconnects is the damascene process, which requires the filling of embedded trenches and/or vias.
A typical damascene process for producing a multilevel structure having feature sizes in the range of 0.5 micron (.mu.) or less would include: blanket deposition of a dielectric material; patterning of the dielectric material to form openings; deposition of a conductive material onto the substrate in sufficient thickness to fill the openings; and removal of excessive conductive material from the substrate surface using a chemical reactant-based process, mechanical method, or combined chemical-mechanical polishing techniques. Currently the conductive material is typically deposited using chemical vapor deposition (CVD), evaporation, and sputtering.
Copper fill of a feature such as a trench or via using chemical vapor deposition (CVD) tends to create voids in the center of the filled opening, because CVD provides a conformal layer over the interior surface of the trench or via and eventually small voids are entrapped as some areas of the feature interior surface grow to touch each other. This is particularly true with regard to high aspect ratio features. Further, contaminants from the deposition source are frequently found in the deposited conductive material. Evaporation is successful in covering shallow features, but is generally not practical for the filling of high aspect ratio features.
Sputtered copper may be used to provide copper fill, if used in combination with a reflow of the copper to avoid the formation of voids which may otherwise occur along the sidewalls of the openings. A typical sputtering technique for filling of high aspect ratio features of less than about 0.5 .mu.m includes cold (typically below about 150.degree. C.) deposition of sputtered copper over the feature surface (which commonly comprises a silicon oxide base overlaid by a barrier layer such as tantalum, which is further overlaid by a seed layer of copper having the desired crystalline orientation). The cold deposition of the sputtered copper layer promotes adhesion of the copper to the substrate surface. The cold sputter deposition is followed by an annealing process (without deposition) at temperatures in excess of about 400.degree. C., to reflow the copper and obtain filling of the trench or via. However, such a reflow process typically requires hours, due to the low bulk diffusivity of copper.
Although use of a reflow process to fill features such as trenches and vias is the simplest method of filling, present conventional processes require either a particularly high temperature (about 450.degree. C. or higher, for example) or a long reflow time (typically about 15 minutes or longer). As the feature size of semiconductor patterned metal features has become increasingly smaller, the danger of trapping void spaces within the copper fill volume during the reflow process has increased.
U.S. Pat. No. 5,246,885 to Braren et al., issued Sep. 21, 1993, describes the problems listed above, and proposes the use of a laser ablation system for the filling of high aspect ratio features. Alloys, graded layers, and pure metals are deposited by ablating targets comprising more than one material using a beam of energy to strike the target at a particular angle. The ablated material is said to create a plasma composed primarily of ions of the ablated material, where the plasma is translated with high directionality toward a surface on which the material is to be deposited. The preferred source of the beam of energy is a UV laser. The heating of the deposition surface is limited to the total energy deposited by the beam, which is said to be minimal.
U.S. Pat. No. 5,312,509 of Rudolph Eschbach, issued May 17, 1974, discloses a manufacturing system for low temperature chemical vapor deposition of high purity metals. In particular, a semiconductor substrate including etched patterns is plasma cleaned; subsequently, the substrate is coated with adhesion and nucleation seed layers. A reactor connected to the process chamber containing the substrate sublimes a precursor of the metal to be deposited, which is then transported to the substrate. A reactor heat transfer system provides selective reactor cooling and heating above and below the precursor sublimation temperature under the control of programmable software. The heated chuck on which the substrate sits heats the substrate above the dissociation temperature of the precursor, releasing the metal from the precursor onto the substrate to nucleate the metal species onto the seed layer on the substrate. Although an adhesion barrier layer (and a sputtered seed layer if required) are said to be deposited using sputter deposition, the copper layer is applied solely by CVD deposition, to avoid the sidewall voiding which is said to occur if sputtering is used for the copper deposition.
U.S. Pat. No. 5,354,712 to Ho et al., issued Oct. 11, 1994, describes a method for forming interconnect structures for integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the side-walls and bottom of interconnect trenches defined in a dielectric layer. Subsequently, a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench. The metal layer comprises copper which is, deposited by chemical vapor deposition from an organo-metallic precursor at low temperatures. In particular, the layer of copper is deposited by CVD from copper (hexafluoroacetylacetonate)trimethyl vinylsilane compound by pyrolysis at low temperatures. This process suffers the problem of voids forming in the center of the filled opening, as previously described, and from the presence of contaminant residues from the precursor material which remain in the deposited metallic fill.
U.S. Pat. No. 5,585,673, issued to Joshi et al. on Dec. 17, 1996, discloses refractory metal capped low resistivity metal conductor lines and vias. In particular, the low resistivity metal is deposited using physical vapor deposition (e.g., evaporation or collimated sputtering), followed by chemical vapor deposition (CVD) of a refractory metal cap. Recommended interconnect metals include Al.sub.x Cu.sub.y (wherein the sum of x and y is equal to one and both x and y are greater than or equal to zero). The equipment required for collimated sputtering is generally difficult to maintain and difficult to control, since there is a constant build up of sputtered material on the collimator over time. Collimated sputtering is described in U.S. Pat. No. 5,478,455 to Actor et al., issued Dec. 26, 1995. Collimation, whether for sputtering or evaporation, is inherently a slow deposition process, due to the reduction in sputtered flux reaching the substrate.
It would be highly desirable to have a method for filling of semiconductor interconnect features which does not require the use of particularly complex equipment; which provides good step coverage for small, high aspect ratio features, while avoiding void formation; which can be carried out at temperatures below about 450.degree. C.; and, which does not require a long processing time (in excess of about 15 minutes).